Semiconductor devices (such as integrated circuits) are generally fabricated on a substrate of silicon known as a wafer. A single wafer typically includes a large number of devices (such as integrated circuits) that are grouped into units called dies. A single wafer typically has a plurality of dies formed thereon. Each die is later singulated from the wafer and further processed and packaged. Modern technology typically uses 8-inch (200-mm) diameter wafers, and is moving to 12-inch (300-mm) wafers. Essentially every single device fabricated on a wafer needs to be electrically tested by probing. Probing more than one device at a time is particularly advantageous. Modern probing equipment can probe 32 or more semiconductor devices at the same time. However, this is often only a small fraction of the total number of devices on a wafer. There has been great interest in developing a probing system that can contact more, preferably all devices on a wafer at the same time.
It is generally desirable to identify which of the plurality of dies on a wafer are good prior to their packaging, and preferably prior to their, being singulated from the wafer. To this end, a wafer “tester” or “prober” may be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond pads) on the dies. In this manner, the semiconductor dies can be tested, prior to singulating the dies from the wafer.
Typically, semiconductor devices are exercised (burned-in and tested) only after they have been singulated (separated) from the wafer and have gone through another long series of “back-end” process steps in which they are assembled into their final “packaged” form. The added time and expense of singulating and packaging the device goes to waste if the final “packaged” device is found to be defective after packaging. Consequently, performing testing or burn-in of semiconductor devices prior to their being singulated from the wafer has been the object of prolonged endeavor.
Modern integrated circuits include many thousands of transistor elements, for example, with many hundreds of bond pads disposed in close proximity to one another; e.g., 4 mils (about 100 μ) center-to-center. One common layout of the bond pads has one or more rows of bond pads disposed close to the peripheral edges of the die. Another common layout has is called “lead on center” (LOC) with typically a single row of contacts along a center line of a die. Other layouts, some irregular, are not uncommon. The proximity and number of pads is a challenge to the technology of probing devices.
Generally, probing devices for testing semiconductor devices on a wafer have involved providing a single test substrate with a plurality of contact elements for contacting corresponding pads on the wafer being tested. To test a full wafer simultaneously generally requires extremely complex interconnection substrates, which may easily include tens of thousands of such contact elements. As an example, an 8-inch wafer may contain 500 16 Mb DRAMs, each having 60 bond pads, for a total of 30,000 connections between the wafer under test (WUT) and the test electronics. Earlier solutions included mating with some subset of these connections to support limited or specialized testing. It would be advantageous to fully connect an entire wafer.
Moreover, the fine pitch requirements of modern semiconductor devices require extremely high tolerances to be maintained when bringing the test substrate together with the wafer being tested. During testing or burn-in processes, heat is produced which causes thermal expansion of the underlying substrate materials. Thermal expansion presents a further challenge to connecting a test substrate to the WUT because of the extremely tight tolerances and close spacing of pads.
To effect reliable pressure connections between contact elements and, e.g., a semiconductor device, one must be concerned with several parameters including, but not limited to: alignment, probe force, overdrive, contact force, balanced contact force, scrub, contact resistance, and planarization. A general discussion of these parameters may be found in U.S. Pat. No. 4,837,622, entitled “High Density Probe Card,” incorporated by reference herein, which discloses a high density epoxy ring probe card including a unitary printed circuit board having a central opening adapted to receive a preformed epoxy ring array of probe elements.
A more sophisticated probe card uses resilient spring elements to make contact with a device on a wafer. Commonly assigned U.S. Pat. No. 5,806,181, entitled “Contact Carriers for Populating Larger Substrates with Spring Contacts,” issued Sep. 15, 1998, ('181 patent), incorporated by reference herein, discloses such a probe card. The resilient spring elements of the '181 patent are pre-fabricated on individual spring contact carriers (“tiles”).
The resilient spring elements can alternatively be prefabricated on the wafer itself. This configuration is known as MOST Technology, using Microspring Contacts On Silicon. Such a wafer is conveniently manufactured using techniques described in commonly assigned, U.S. patent application Ser. No. 08/558,332, entitled “Method of Mounting Resilient Contact Structures to Semiconductor Devices,” filed Nov. 15, 1995, incorporated by reference herein. A contactor or testing substrate that can perform a wafer-level test or burn-in procedure on a MOST wafer must provide corresponding conductive areas that can precisely align with the thousands of microsprings disposed on the wafer.
Providing a contactor that can be precisely aligned with each of the resilient spring elements or bond pads is challenging because of tolerances and the expansion of the underlying substrate materials due to heat produced during the testing or burn-in processes. Also, providing a large size contactor that has corresponding conductive areas for each spring element on the wafer under test can be problematic because if one of the thousands of conductive areas is defective, the entire contactor will be deemed defective.
Thus, what is needed is a segmented contactor that provides separate contactor units for performing wafer-level testing or burn-in procedures and that minimizes problems related to tolerances and thermal expansion.